| 전자부품 데이터시트 검색엔진 |
|
CS5378 데이터시트(PDF) 23 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS5378 데이터시트(HTML) 23 Page - Cirrus Logic |
|
23 / 88 page ![]() CS5378 DS639F2 23 6.4 Master Clock Jitter and Skew Care must be taken to minimize jitter and skew on the distributed system clock as both parameters af- fect measurement performance. Jitter on the input clock causes jitter in the generat- ed modulator clock, resulting in sample timing er- rors and increased noise. Skew between input clocks from node to node cre- ates a sample timing offset, resulting in systematic measurement errors in a reconstructed signal. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |