CS42436-DMZ datasheet(45/61 Pages) CIRRUS

45 / 61 page

DS647F2

CS42436

7.6.5

ADC2 Single-Ended Mode (ADC2 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC2

1 - Enabled; Single-Ended input to ADC2

Function:

When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. A

+6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driv-

en to the common mode of the ADC. See Figure 21 on page 50 for a graphical description.

7.6.6

ADC3 Single-Ended Mode (ADC3 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC

1 - Enabled; Single-Ended input to ADC

Function:

When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differential

input. When enabled, this bit allows the user to choose between four single-ended inputs to ADC3, using

the AIN5_MUX and AIN6_MUX bits. See Figure 11 on page 31 and Figure 21 on page 50 for graphical

descriptions.

7.6.7

Analog Input Ch. 5 Multiplexer (AIN5_MUX)

Default = 0

0 - Single-Ended Input AIN5A

1 - Single-Ended Input AIN5B

Function:

ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit

selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in Single-Ended Mode. This bit

is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 31 for a graphical description.

7.6.8

Analog Input Ch. 6 Multiplexer (AIN6_MUX)

Default = 0

0 - Single-Ended Input AIN6A

1 - Single-Ended Input AIN6B

Function:

ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX bit

selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in Single-Ended Mode. This bit

is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 31 for a graphical description.

CS42436-DMZ 데이터시트(PDF) 45 Page - Cirrus Logic