CS42436-DMZ datasheet(49/61 Pages) CIRRUS

49 / 61 page

DS647F2

CS42436

7.12

ADC Channel Invert (Address 17h)

7.12.1

Invert Signal Polarity (INV_AINX)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

7.13

Status (Address 19h) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated

mask register will always be “0” in this register.

7.13.1

CLOCK ERROR (CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active

during the error condition. See “System Clocking” on page 33 for valid clock ratios.

7.13.2

ADC Overflow (ADCX_OVFL)

Default = x

Function:

Indicates that there is an over-range condition anywhere in the CS42436 ADC signal path of each of the

associated ADC’s.

7.14

Status Mask (Address 1Ah)

Default = 0000

Function:

The bits of this register serve as a mask for the error sources found in the register “Status (Address 19h)

(Read Only)” on page 49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will

affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not

affect status register. The bit positions align with the corresponding bits in the Status register.

432

Reserved

INV_AIN6

INV_AIN5

INV_AIN4

INV_AIN3

INV_AIN2

INV_AIN1

Reserved

CLK Error

ADC3_OVFL

ADC2_OVFL

ADC1_OVFL

Reserved

CLK Error_M

ADC3_OV

FL_M

ADC2_OVFL_M

ADC1_OVFL_M

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