CS42888-CQZ datasheet(49/61 Pages) CIRRUS

49 / 61 page

DS717F2

CS42888

6.12

ADC Channel Invert (Address 17h)

6.12.1

Invert Signal Polarity (INV_AINX)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

6.13

Status Control (Address 18h)

6.13.1

Interrupt Pin Control (INT[1:0])

Default = 00

00 - Active high; high output indicates interrupt condition has occurred

01 - Active low, low output indicates an interrupt condition has occurred

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.

11 - Reserved

Function:

Determines how the Interrupt pin (INT) will indicate an interrupt condition.

For DAC and ADC clock errors, the INT pin is set to “Level Active Mode” and will become active during

the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become active

during the overflow error.

6.14

Status (Address 19h) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated

mask register will always be “0” in this register.

6.14.1

DAC CLOCK ERROR (DAC_CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes

active during the error condition. See “System Clocking” on page 29 for valid clock ratios.

432

Reserved

INV_AIN4

INV_AIN3

INV_AIN2

INV_AIN1

432

Reserved

INT1

INT0

Reserved

DAC_CLK Error

ADC_CLK Error

Reserved

ADC2_OVFL

ADC1_OVFL

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