SC471AEVB datasheet(15/27 Pages) SEMTECH

15 / 27 page

SC471/SC471A

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POWER MANAGEMENT

This current sensing scheme actually regulates the

inductor valley current, (see Figure 11). This means that

if the current limit is set to 10A, the peak current through

the inductor would be 10A plus the peak ripple current,

and the average current through the inductor would be

10A plus 1/2 the peak-to-peak ripple current.

I LIMIT

ILOAD

IPEAK

TIME

Valley Current Limit

Figure 11

The RDSON sensing circuit is shown in Figure 12 with

RILIM = R1 and RDSON of Q2.

VOUT

+5V

VBAT

GND

VDD

ILIM

BST

SC471/A

Figure 12

The resistor sensing circuit is shown in Figure 13 with

RILIM = R1 and RSENSE = R4.

Vout

+5V

GND

VDD

ILIM

BST

VBAT

SC471/A

Figure 13

For resistor sensing, the current through the lower MOSFET

and the source sense resistor develops a voltage that

opposes the voltage developed across RILIM. When the

voltage developed across the RSENSE resistor reaches

voltage drop across RILIM, an over-current exists and the

high-side MOSFET will not be allowed to turn on.

The following over-current equation can be used for both

RDSON or resistive sensing. For RDSON sensing, the

MOSFET RDSON rating is used for the value of RSENSE.

SENSE

ILIM

Valley

Power Good Output

The power good (PGD) output is an open-drain output

which requires a pull-up resistor.

When the output

voltage as sensed at FB is -20% from the 0.75V reference

(600mV), PGD is pulled low. It is held low until the output

voltage returns above -20% of nominal. PGD is held low

during start-up and will not be allowed to transition high

until soft-start is completed when FB reaches 0.75V.

There is a 5μs delay built into the PGD circuit to prevent

false transitions.

PGD also transitions low if the FB pin exceeds +20% of

nominal, which is also the over-voltage shutdown point.

Applications Information (continued)

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