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F75111RG 데이터시트(PDF) 21 Page - Feature Integration Technology Inc. |
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F75111RG 데이터시트(HTML) 21 Page - Feature Integration Technology Inc. |
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21 / 45 page ![]() July, 2007 V0.27P - 19 - F75111 7.17 GPIO1x Pulse Inverse Register – Index 17h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP17_PULSINV R/W VSB3V GPIO 17 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 6 GP16_PULSINV R/W VSB3V GPIO 16 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 5 GP15_PULSINV R/W VSB3V GPIO15 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 4 GP14_PULSINV R/W VSB3V GPIO14 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 3 GP13_PULSINV R/W VSB3V GPIO13 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 2 GP12_PULSINV R/W VSB3V GPIO12 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. If this pin services as IRQ/SMI#, this bit has no effect. 1 GP11_PULSINV R/W VSB3V GPIO 11 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 0 GP10_PULSINV R/W VSB3V GPIO10 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 7.18 GP1X Edge Detector Enable Register – Index 0x18 Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 EN_GP17EDGE R/W VSB3V Enable GPIO17 Edge Detector. If this bit set to 1 and GPIO17 set to |
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