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F75111RG 데이터시트(PDF) 29 Page - Feature Integration Technology Inc. |
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F75111RG 데이터시트(HTML) 29 Page - Feature Integration Technology Inc. |
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29 / 45 page ![]() July, 2007 V0.27P - 27 - F75111 CR24. 1 GP21_PULSINV R/W VSB3V GPIO 21 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 0 GP20_PULSINV R/W VSB3V GPIO20 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 7.31 GP2x Edge Detector Enable Register – Index 0x28 Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 EN_GP27EDGE R/W VSB3V Enable GPIO27 Edge Detector. If this bit set to 1 and GPIO17 set to input mode [CR10] will enable GPIO27 edge detection. Default is disabled. 6 EN_GP26EDGE R/W VSB3V Enable GPIO26 Edge Detector. If this bit set to 1 and GPIO16 set to input mode [CR10] will enable GPIO26 edge detection. Default is disabled. 5 EN_GP25EDGE R/W VSB3V Enable GPIO25 Edge Detector. If this bit set to 1 and GPIO15 set to input mode [CR10] will enable GPIO25 edge detection. Default is disabled. 4 EN_GP24EDGE R/W VSB3V Enable GPIO24 Edge Detector. If this bit set to 1 and GPIO14 set to input mode [CR10] will enable GPIO24 edge detection. Default is disabled. 3 EN_GP23EDGE R/W VSB3V Enable GPIO23 Edge Detector. If this bit set to 1 and GPIO13 set to input mode [CR10] will enable GPIO23 edge detection. Default is disabled. 2 EN_GP22EDGE R/W VSB3V Enable GPIO22 Edge Detector. If this bit set to 1 and GPIO12 set to input mode [CR10] will enable GPIO22 edge detection. Default is disabled. 1 EN_GP21EDGE R/W VSB3V Enable GPIO21 Edge Detector. If this bit set to 1 and GPIO11 set to input mode [CR10] will enable GPIO21 edge detection. Default is disabled. 0 EN_GP20EDGE R/W VSB3V Enable GPIO20 Edge Detector. If this bit set to 1 and GPIO10 set to input mode [CR10] will enable GPIO20 edge detection. Default is |
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