AT52SC1283J datasheet(19/52 Pages) ATMEL

19 / 52 page

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

Notes:

1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS

FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A22 through A8 are don’t care.

2. PA is the plane address (A22 - A18). Any address within a plane can be used.

3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 23 - 27 for

details).

4. The first bus cycle address should be the same as the word address to be programmed.

5. This fast programming option enables the user to program two words in parallel only when V

PP = 10V. The addresses, Addr0

and Addr1, of the two words, D

IN0 and DIN1, must only differ in address A0. This command should be used during manufac-

turing purposes only.

6. During the second bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address

PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H and 00008AH - 000109H.

7. The plane address should be the same during the first and second bus cycle.

8. The status register bits are output on I/O7 - I/O0.

9. Any address within the user programmable protection register region. Please see “Protection Register Addressing Table” on

page 20.

10. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

11. D

OUT represents 16 bits of data. If all data bits are “0s”, the register is locked.

12. See “Burst Configuration Register” on page 21. Bits B15 - B0 of the burst configuration register determine A15 - A0.

Addresses A16 - A22 can select any plane.

Command Definition Table

Command Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

Addr

Data

Addr

Data

Addr

Data

Read

(2)

Chip Erase

Addr

Plane Erase

Addr

Sector Erase

(3)

Word Program

Addr

(4)

40/10

Addr

(4)

DIN

Dual Word Program

(5)

Addr0

IN0

Addr1

IN1

Erase/Program Suspend

Erase/Program Resume

(2)

Product ID Entry

(6)(7)

1PA

(2)

Sector Softlock

(3)

Sector Hardlock

(3)

Sector Unlock

(3)

Read Status Register

(2)

(7)

OUT

(8)

Clear Status Register

Program PR0 (Block B) or PR1

Addr

(9)

Addr

(9)

Lock Protection PR0 – Block B

FFFD

Lock Protection PR1

0000

Status of Protection PR0 (Block B)

000080

OUT

(10)

Status of Protection PR1

000089

OUT

(11)

Program Burst Configuration Register

(7)+Addr(12)

Read Burst Configuration Register

(7)

PAX005

(7)

OUT

CFI Query

AT52SC1283J 데이터시트(PDF) 19 Page - ATMEL Corporation

AT52SC1283J 데이터시트(HTML) 19 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

데이터시트 다운로드

링크 URL