LT3751EUFD datasheet(22/28 Pages) LINER

22 / 28 page

LT3751

3751f

APPLICATIONS INFORMATION

Large Signal Stability

Large signal stability can be an issue when audible noise

is a concern. Figure 13 shows that the problem originates

from the one-shot clock and the output voltage ripple. The

load must be constrained such that the output voltage

ripple does not exceed the regulation range of the error

ampliﬁer within one clock period (approximately 6mV

referred to the FB pin).

The output capacitance should be increased if oscillations

occur or audible noise is present. Use Figure 14 to deter-

mine the maximum load for a given output capacitance to

maintain low audible noise operation. A small capacitor

can also be added from the FB pin to ground to lower the

ripple injected into FB pin.

Small Signal Stability

The LT3751’s error ampliﬁer is internally compensated to

increase its operating range but requires the converter’s

output node to be the dominant pole. Small signal stability

constraints become more prevalent during high-load-

ing conditions where the dominant output pole moves

to higher frequency and closer to the internal feedback

poles and zeros. The feedback loop requires the output

pole frequency to remain below 200Hz to guarantee small

signal stability. This allows smaller RLOAD values then the

large signal constraint. Thus, small signal issues should

not arise if the large signal constraint is met.

Figure 14. COUT(MIN) vs Output Power

OUTPUT POWER (W)

150

3751 F14

200

100

VOUT = 150V

VOUT = 300V

VOUT = 600V

Figure 13. Voltage Ripple Stability Constraint

VOUT

3751 F13

26kHz

ONE-SHOT

CLK

IPRI

LOAD

DROOP

LT3751EUFD 데이터시트(PDF) 22 Page - Linear Technology

LT3751EUFD 데이터시트(HTML) 22 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

데이터시트 다운로드

링크 URL