LT3751EUFD datasheet(4/28 Pages) LINER

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LT3751

3751f

ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual 25kΩ

resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

UVLO1 Threshold

Measured from Pin to GND

1.195

1.225

1.255

UVLO2 Threshold

Measured from Pin to GND

1.195

1.225

1.255

OVLO1 Threshold

Measured from Pin to GND

1.195

1.225

1.255

OVLO2 Threshold

Measured from Pin to GND

1.195

1.225

1.255

Gate Minimum High Time

0.7

μs

Gate Peak Pull-Up Current

VCC = 5V, LVGATE Active

VCC = 12V, LVGATE Inactive

2.0

1.5

Gate Peak Pull-Down Current

VCC = 5V, LVGATE Active

VCC = 12V, LVGATE Inactive

1.2

1.5

Gate Rise Time

10%

→ 90%, CGATE = 3.3nF (Note 8)

VCC = 5V, LVGATE Active

VCC = 12V, LVGATE Inactive

Gate Fall Time

90%

→ 10%, CGATE = 3.3nF (Note 8)

VCC = 5V, LVGATE Active

VCC = 12V, LVGATE Inactive

Gate High Voltage

(Note 8):

VCC = 5V, LVGATE Active

VCC = 12V, LVGATE Inactive

VCC = 12V, LVGATE Inactive, CLAMP Pin = 5V

VCC = 24V, LVGATE Inactive

4.98

10.5

5.6

10.5

11.5

6.5

11.5

Gate Turn-Off Propagation Delay

CGATE = 3.3nF

25mV Overdrive Applied to CSP Pin

180

Gate Voltage Overshoot

500

CLAMP Pin Threshold

1.6

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3751E is guaranteed to meet performance speciﬁcations

from 0°C to 125°C junction temperature. Speciﬁcations over the –40°C

to 125°C operating junction temperature range are assured by design

characterization and correlation with statistical process controls. The

LT3751I is guaranteed over the full –40°C to 125°C operating junction

temperature range.

Note 3: A 60V internal clamp is connected to RVTRANS, RDCM, RVOUT,

UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that

the pin currents do not exceed the Absolute Maximum Ratings.

Note 4: Currents will increase as pin voltages are taken higher than the

internal clamp voltage.

Note 5: Refer to Block Diagram for VTRANS and VDRAIN deﬁnitions.

Note 6: Low noise regulation of the output voltage requires a resistive

voltage divider from output voltage to FB pin. FB pin should not be

grounded in this conﬁguration. Refer to the Typical Application diagram for

proper FB pin conﬁguration.

Note 7: The feedback pin has built-in hysteresis that deﬁnes the boundary

between charge-only mode and low noise regulation mode.

Note 8: LVGATE should be used in parallel with HVGATE when VCC is less

than or equal to 8V (LVGATE active). When not in use, LVGATE should be

tied to VCC (LVGATE inactive).

Note 9: Do not apply a positive or negative voltage or current source to

HVGATE, otherwise permanent damage may occur.

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