PROASIC3E datasheet(9/37 Pages) ACTEL

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I/O Structures in IGLOOe and Pro ASIC3E Devices

v1.4

I/O Bank Structure

Low-power flash device I/Os are divided into multiple technology banks. The number of banks is

device-dependent. The IGLOOe, ProASIC3EL, and ProASIC3E devices have eight banks (two per

side); and IGLOO, ProASIC3L, and ProASIC3 devices have two to four banks. Each bank has its own

VCCI power supply pin. Multiple I/O standards can co-exist within a single I/O bank.

In IGLOOe, ProASIC3EL, and ProASIC3E devices, each I/O bank is subdivided into VREF minibanks.

These are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All I/Os in a given

minibank share a common VREF line (only one VREF pin is needed per VREF minibank). Therefore, if

an I/O in a VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be

able to use the voltage assigned to that pin. If the location of the VREF pin is selected manually in

the software, the user must satisfy VREF rules (refer to I/O Software Control in Low-Power Flash

Devices). If the user does not pick the VREF pin manually, the software automatically assigns it.

Figure 4 is a snapshot of a section of the I/O ring, showing the basic elements of an I/O tile, as

viewed from the Designer place-and-route tool’s MultiView Navigator (MVN).

Low-power flash device I/Os are implemented using two tile types: I/O and differential I/O (diffio).

The diffio tile is built up using two I/O tiles, which form an I/O pair (P side and N side). These I/O

pairs are used according to differential I/O standards. Both the P and N sides of the diffio tile

include an I/O buffer and two I/O logic blocks (auxiliary and main logic).

Every minibank (E devices only) is built up from multiple diffio tiles. The number of the minibank

depends on the different-size dies. Refer to the "Pro I/Os—IGLOOe, ProASIC3EL, and ProASIC3E"

section on page 3 for an illustration of the minibank structure.

Figure 5 on page 10 shows a simplified diagram of the I/O buffer circuitry. The Output Enable signal

(OE) enables the output buffer to pass the signal from the core logic to the pin. The output buffer

contains ESD protection circuitry, an n-channel transistor that shunts all ESD surges (up to the limit

of the device ESD specification) to GND. This transistor also serves as an output pull-down resistor.

Each output buffer also contains programmable slew rate, drive strength, programmable power-up

state (pull-up/-down resistor), hot-swap, 5 V tolerance, and clamp diode control circuitry. Multiple

flash switches (not shown in Figure 5 on page 10) are programmed by user selections in the

software to activate different I/O features.

Figure 4 • Snapshot of an I/O Tile

I/O Pad/Buffer I/O Logic (assigned)

N Side

(assigned)

P Side

(unassigned)

Diffio Tile

Minibank

Other

Minibanks

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