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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AX2000-1CGG896 데이터시트(PDF) 39 Page - Actel Corporation |
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AX2000-1CGG896 데이터시트(HTML) 39 Page - Actel Corporation |
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39 / 226 page  Axcelerator Family FPGAs v2.7 2-25 LVTTL Output Drive Strength = 2 (12mA) / High Slew Rate tDP Input Buffer 1.72 1.96 2.31 ns tPY Output Buffer 3.34 3.80 4.47 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns LVTTL Output Drive Strength =3 (16mA) / High Slew Rate tDP Input Buffer 1.72 1.96 2.31 ns tPY Output Buffer 3.16 3.60 4.24 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns Table 2-21 • 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C (Continued) '–2' Speed '–1' Speed 'Std' Speed Parameter Description Min. Max. Min. Max. Min. Max. Units |
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