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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AX2000-1CSG896I 데이터시트(PDF) 76 Page - Actel Corporation |
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AX2000-1CSG896I 데이터시트(HTML) 76 Page - Actel Corporation |
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76 / 226 page  Axcelerator Family FPGAs 2- 62 v2.7 Implementation Example: Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2 output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both CLKF and CLKG global resources. Figure 2-45 • Example of HCLKA driven from a PLL with External Clock Source Figure 2-46 • Example of PLLINT and PLLOUT Usage Figure 2-47 • Complex Clock Distribution Example HCLKAP HCLKAN PLLHCLK HCLKA Network CLK1 CLK2 FB RefCLK PLLA PLLINT PLLHCLK PLLOUT HCLKA Network CLK1 CLK2 FB RefCLK PLLA Logic Logic CLK1 CLK2 FB RefCLK PLLF CLK1 CLK2 FB RefCLK PLLE PLLINT INBUF Non-Clock Pins P N PLLRCLK PLLOUT PLLRCLK PLLRCLK CLKE Logic CLKF CLKG CLKINT |
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