This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

10

EN25F05

Rev. B, Issue Date: 2008/06/23

Figure 7. Read Status Register Instruction Sequence Diagram

Table 6. Status Register Bit Locations

S7

S6

S5

S4

S3

S2

S1

S0

SRP

0

0

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:

WIP bit.

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no

such cycle is in progress.

WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is

reset and no Write Status Register, Program or Erase instruction is accepted.

BP2, BP1, BP0 bits.

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size

of the area to be software protected against Program and Erase instructions. These bits are written

with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1,

BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against

Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2,

BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The

Chip Erase (CE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.

Status Register Protect

Reserved Bits

Block Protect Bits

Write Enable Latch

Write In Progress