This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

12

EN25F05

Rev. B, Issue Date: 2008/06/23

Figure 8. Write Status Register Instruction Sequence Diagram

Read Data Bytes (READ) (03h)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during

the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on

Serial Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling

edge of Serial Clock (CLK).

The instruction sequence is shown in Figure 9. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When

the highest address is reached, the address counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip

Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any

effects on the cycle that is in progress.

Figure 9. Read Data Instruction Sequence Diagram