Altera Corporation

11

Configuration Devices for SRAM-Based LUT Devices Data Sheet

nCASC

(6)

6

12

15

Output

Cascade select output (active low). This output goes

low when the address counter has reached its

maximum value. In a chain of EPC1 or EPC2 devices,

the nCASC pin of one device is connected to the nCS pin

of the next device, which permits DCLK to clock data

from the next EPC1 or EPC2 device in the chain.

nINIT_CONF

(5), (7)

–

13

16

Open-

Drain

Output

Allows the INIT_CONF JTAG instruction to initiate

configuration. This pin is connected to the nCONFIG pin

of the LUT device to initiate configuration from the

EPC2 via a JTAG instruction. If multiple EPC2 devices

are used to configure an ACEX, APEX, FLEX or

Mercury device, only the first EPC2 has its

nINIT_CONF

pin tied to the device’s nCONFIG pin.

TDI

(7)

–

11

13

Input

JTAG circuitry is not used.

TDO

(7)

–

1

28

Output

JTAG data output pin. Do not connect this pin if the

JTAG circuitry is not used.

TMS

(7)

–

19

25

Input

JTAG circuitry is not used.

TCK

(7)

–

3

32

Input

JTAG clock pin. Connect this pin to ground if the JTAG

circuitry is not used.

VCCSEL

(7)

–53Input

connected to ground if the device uses a 5.0-V power

VPPSEL

(7)

–

14

17

Input

Mode select for VPP. VPPSEL must be connected to

ground if VPP uses a 5.0-V power supply

if VPP uses a 3.3-V power supply (i.e, VPP = 3.3 V).

VPP

(7)

–

18

23

Power

Programming power pin. For the EPC2 device, this pin

can be tied to 5.0 V to improve in-system programming

times. For EPC1 and EPC1441 devices, VPP must be

Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K

& FLEX 6000 Configuration (Part 2 of 3)

Pin Name

Pin Number

Pin

Type

Description

8-Pin

20-Pin

PLCC

32-Pin