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EPC4 데이터시트(PDF) 18 Page - Altera Corporation |
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EPC4 데이터시트(HTML) 18 Page - Altera Corporation |
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18 / 36 page ![]() 18 Altera Corporation Configuration Devices for SRAM-based LUT Devices Data Sheet Table 5 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC1 and EPC1441 devices at 3.3 V. Notes to Table 5: (1) For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. (2) The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. Table 5. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC1 & EPC1441 Devices at 3.3 V Note (1) Symbol Parameter Min Max Units tPOR POR delay (2) 200 ms tOEZX OE high to DATA output enabled 80 ns tCH DCLK high time 50 250 ns tCL DCLK low time 50 250 ns tDSU Data setup time before rising edge on DCLK 30 ns tDH Data hold time after rising edge on DCLK 0ns tCO DCLK to DATA out 30 ns tOEW OE low pulse width to guarantee counter reset 100 ns fCLK DCLK frequency 2 10 MHz |
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