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CDK1300 데이터시트(PDF) 4 Page - Cadeka Microcircuits LLC.

부품명 CDK1300
상세설명  8-bit, 250 MSPS ADC with Demuxed Outputs
PDF  12 Pages
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제조업체  CADEKA [Cadeka Microcircuits LLC.]
홈페이지  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

CDK1300 데이터시트(HTML) 4 Page - Cadeka Microcircuits LLC.

  CDK1300 Datasheet HTML 1Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 2Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 3Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 4Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 5Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 6Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 7Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 8Page - Cadeka Microcircuits LLC. CDK1300 Datasheet HTML 9Page - Cadeka Microcircuits LLC. Next Button
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©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
symbol
parameter
conditions
Min
typ
Max
units
Resolution
8
bits
DC Performance
DLE
Differential Linearity Error
+25°C, ƒIN = 1KHz
-0.7/1.05
LSB
-40°C to +85°C, ƒIN = 1KHz
-0.95/+1.5
LSB
ILE
Integral Linearity Error
+25°C, ƒIN = 1KHz
±1.7
LSB
-40°C to +85°C, ƒIN = 1KHz
±2.25
LSB
No Missing Codes
@250 MSPS, ƒIN = 1KHz
Guaranteed
Analog Input
Input Voltage Range
with respect to VIN-
±470
mVpp
VCM
Input Common Mod(2)
2.3
2.5
2.0
V
Input Bias Current
+25°C
10
µA
Input Resistance
+25°C
50
kΩ
Input Capacitance
+25°C
4
pF
Input Bandwidth
+25°C (-3dB of FS)
220
MHz
Gain Error
+25°C
2
%
Offset Error
+25°C
±10
mV
PSRR
Offset Power Supply Rejection Ratio
AVcc = 5V ±0.25V
0.5
mV/V
Timing Characteristics
Conversion Rate(1)
250
MSPS
tpd1
Output Delay (Clock-to-Data)(2)
-40°C to +85°C
6
8
10.5
ns
Output Delay Tempco
22
ps/°C
tap
Aperture Delay Time
0.5
ns
Aperture Jitter Time
2.0
ps-RMS
Pipeline Delay (Latency)
Single Channel Mode
2.5
Cycle
Demuxed Interleaved Mode
2.5
Cycle
Demuxed Parallel Mode
Channel B
2.5
Cycle
Channel A
3.5
Cycle
CLK to DCLKOUT Delay Time
tpd2
Single Channel Mode(2)
4
6
7
ns
tpd3
Dual Channel Mode(2)
5.3
6.16
7.8
ns
Dynamic Performance
ENOB
Effective Number of Bits
ƒIN = 70MHz, +25°C(1)
5.8
6.4
Bits
ƒIN = 70MHz, -40°C to +85°C(2)
5.5
6.0
Bits
SNR
Signal-to-Noise Ratio
ƒIN = 70MHz, +25°C(1)
42
43
dB
ƒIN = 70MHz, -40°C to +85°C(2)
36
40
dB
THD
Total Harmonic Distortion
ƒIN = 70MHz, +25°C(1)
-43
-40
dB
ƒIN = 70MHz, -40°C to +85°C(2)
-42
-37
dB
SINAD
Signal-to-Noise and Distortion
ƒIN = 70MHz , +25°C(1)
37
40
dB
ƒIN = 70MHz, -40°C to +85°C(2)
35
38
dB
notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.



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