©2008 CADEKA Microcircuits LLC

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8

Data Sheet

Theory of Operation

The CDK1301 is a three-step subranger. It consists of

two THAs in series at the input, followed by three ADC

blocks. The first block is a three-bit folder with over/under

range detection. The second block consists of two single-

bit folding interpolator stages. There are pipelining THAs

between each ADC block.

The analog decode functions are the input buffer, input

THAs, three-bit folder, folding interpolators, and pipelining

THAs. The input buffer enables the part to withstand rail-

to-rail input signals without latchup or excessive currents

and also performs single-ended to differential conversion.

All of the THAs have the same basic architecture. Each

has a differential pair buffer followed by switched emitter

followers driving the hold capacitors. The input THA also

has hold mode feedthrough cancellation devices.

The three MSBs of the ADC are generated in the first

threebit folder block, the output of which drives a dif-

ferential reference ladder which also sets the full-scale

input range. Differential pairs at the ladder taps gener-

ate midscale, quarter and three-quarter scale, overrange,

and underrange. Every other differential pair collector is

cross-coupled to generate the eighth scale zero crossings.

The middle ADC block generates two bits from the folded

signals of the previous stages after pipeline THAs. Its out-

puts drive more pipeline THAs to push the decoding of the

three LSBs to the next half clock cycle. The three LSBs are

generated in interpolators that are latched one full clock

cycle after the MSBs.

The digital decode consists of comparators, exclusive of

cells for gray to binary decoding, and/or cells used for

mostly over/under range logic. There is a total of 2.5

clock cycles latency before the output bank selection. In

order to reduce sparkle codes and maintain sample rate,

no more than three bits at a time are decoded in any half

clock cycle.

The output data mode is controlled by the state of the

demux mode inputs. There are three output modes:

All data on bank A with clock rate limited to one-half

maximum

Interleaved mode with data alternately on banks A and

B on alternate clock cycles

Parallel mode with bank A delayed one cycle to be

synchronous with bank B every other clock cycle

If necessary, the input clock is divided by two. The

divided clock selects the correct output bank. The user

can synchronize with the divided clock to select the

desired output bank via the differential RESET input.

The output logic family is CMOS with output OVDD supply

adjustable from 2.7V to 5.25V. There are also differential

clock output pins that can be used to latch the output data

in single bank mode or to indicate the current output bank

in demux mode.

Finally, a power-down mode is available, which causes the

outputs to become tri-state, and overall power is reduced

to about 24mW. There is a 2V reference to supply com-

mon mode for single-ended inputs that is not shut down

in powerdown mode.

Figure 1. Single Mode Timing Diagram