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KH561AI 데이터시트(PDF) 7 Page - Cadeka Microcircuits LLC. |
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KH561AI 데이터시트(HTML) 7 Page - Cadeka Microcircuits LLC. |
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7 / 13 page ![]() KH561 DATA SHEET REV. 1A January 2004 7 part, relatively constant performance over supply voltage is achieved. A current sense in the error current leg of the 10X current mirror feeds back to the bias current setup providing a current shutdown feature when the output current approaches 250mA. Figure 2: Simplified Circuit Diagram Developing the Performance Equations The KH561 is intended to provide both a controllable voltage gain from input to output as well as a controllable output impedance. It is best to treat these two operations separately with no load in place. Then, with the no-load gain and output impedance determined, the gain to the load will simply be the no-load gain attenuated by the voltage divider formed by the load and the equivalent output impedance. Figure 3 steps through the output impedance develop- ment using an equivalent model of Figure 2. Offering an equivalent, non-zero, output impedance into a matched load allows the KH561 to operate at lower internal volt- age swings for a given desired swing at the load. This allows higher voltage swings to be delivered at the load for a given power supply voltage at lower distortion levels than an equivalent op amp needing to generate twice the voltage swing actually desired at the matched load. This improved distortion is specified and tested over a wide range as shown in the specification listing. Get both Vo and Io into terms of just the error current, ierr, using: Figure 3: Output Impedance Derivation Note that the Ro expression simplifies considerably if Ri = 0. Also note that if the forward current gain were to go to infinity, the output impedance would go to 0. This would be the normal op amp topology with a very high internal gain. The KH561 achieves a non-zero Ro by setting the internal forward gain to be a low, well controlled, value. Developing the No-Load Gain Expression Taking the output impedance expression as one con- straint setting the external resistor values, we now need to develop the no-load voltage gain expression from the non-inverting input to the output as the other constraint. Figure 4 shows the derivation of the no load gain. Rg Ro ierr Vo Rf Cx 19 Io Io Ibias 10X Current Mirror Current Limit 5pF Q3 Q1 -VCC +VCC 4 Ibias 10X Current Mirror Current Limit 5pF Q4 Q2 +VCC -VCC 21 23 8 Vi ierr Rg Rf if Gierr Ro Vo X1 Ri lo V- + - V i R and ii V R i1 R R VV i R i R R 1 R R Vi R R 1 R R and IGi i i G 1 err i f err g err i g o ff err i f i g o err f i f g o err f err − − − = =+ = + =+ = + + =+ + =+ = + ++ ≡= ++ ++ = + = R R then R V I RR 1 R R G1 R R note that R R G1 R0 i g o o o f i f g i g o f i ierr Rg Rf Gierr Vo X1 Ri V- + - Vi |
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