SN74ACT3631

512

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

11

POST OFFICE BOX 655303

When the port-B data (B0 – B35) outputs are active, the data on the bus comes from the FIFO output register

when the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 data

is always present on the port-A data (A0 – A35) outputs when they are active. The mail1 register flag (MBF1)

is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with

MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read

is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read

and changes only when new data is written to the register.

tpd(R-F)

CLKA

CLKB

RST

0,1

th(FS)

tsu(FS)

th(RS)

tsu(RS)

FS1, FS0

IR

tpd(C-IR)

tpd(C-IR)

OR

tpd(C-OR)

tpd(R-F)

AE

AF

MBF1,

MBF2

tpd(R-F)

Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight