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SN74ACT3631PCB 데이터시트(PDF) 16 Page - Texas Instruments |
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SN74ACT3631PCB 데이터시트(HTML) 16 Page - Texas Instruments |
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16 / 26 page ![]() SN74ACT3631 512 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS246G – AUGUST 1993 – REVISED APRIL 1998 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 (X + 1) Words in FIFO tsu(EN) CLKA AE ENB ENA th(EN) tsu(EN) tsk(2)† tpd(C-AE) X Words in FIFO 1 CLKB 2 tpd(C-AE) th(EN) † tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(2), then AE can transition high one CLKB cycle later than shown. NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L) Figure 8. Timing for AE When FIFO Is Almost Empty (512 – Y) Words in FIFO tpd(C-AF) tpd(C-AF) tsu(EN) CLKA AF ENB ENA tsu(EN) th(EN) [512 – (Y + 1)] Words in FIFO th(EN) tsk(2)‡ 12 CLKB ‡ tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown. NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L) Figure 9. Timing for AF When the FIFO Is Almost Full |
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