SN75ALS173

QUADRUPLE DIFFERENTIAL LINE RECEIVER

SLLS132C – SEPTEMBER 1991 – REVISED MAY 1995

2

POST OFFICE BOX 655303

4B

4A

3B

3A

2B

2A

1B

1A

G

G

4Y

3Y

2Y

1Y

13

11

5

3

15

14

9

10

7

6

1

2

12

4

EN

≥ 1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

logic diagram (positive logic)

4Y

3Y

2Y

1Y

13

11

5

3

15

14

9

10

7

6

1

2

12

4

4B

4A

3B

3A

2B

2A

1B

1A

G

G

schematics of inputs and outputs

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF G OR G ENABLE INPUT

EQUIVALENT OF EACH A OR B INPUT

70

Ω

GND

Output

VCC

GND

Input

VCC

VCC

288 k

Ω

NOM

GND

Input

VCC (A)

or

GND (B)

17 k

Ω

NOM

17 k

Ω

NOM

17 k

Ω

NOM