SN75ALS199

QUADRUPLE DIFFERENTIAL LINE RECEIVER

SLLS046C – JANUARY 1989 – REVISED MAY 1995

2

POST OFFICE BOX 655303

1A

2

1B

1

2A

6

2B

7

3

1Y

5

2Y

4

1, 2EN

EN

1A

2

1B

1

2A

6

2B

7

3

5

4

EN

3A

10

3B

9

4A

14

4B

15

11

3Y

13

4Y

12

3, 4EN

EN

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

12

3, 4EN

2A

6

11

3Y

1Y

3

2

1A

1, 2EN

4

5

2Y

13

4Y

1B

2B

4A

3A

3B

4B

1

7

10

9

14

15

logic diagram

schematics of inputs and outputs

EQUIVALENT OF EACH A OR B INPUT

EQUIVALENT OF EACH ENABLE INPUT

TYPICAL OF ALL OUTPUTS

VCC

Input

VCC

VCC

Input

3 k

Ω

18 k

Ω

300 k

Ω

2 k

Ω

VCC (A)

or

GND (B)

22 k

Ω

Output

50

Ω

40 k

Ω

50

Ω

5 k

Ω

150 k

Ω

1.5 k

Ω

3 k

Ω