THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

22

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

THS0842

CML

R

AIN+

C

VIN+

AIN–

VIN–

REFT

REFB

R

Figure 21. DC-Coupled Differential Input Circuit

For many applications, ac coupling offers a convenient way for biasing the analog input signal at the proper

signal range. Figure 20 shows a typical configuration. To maintain the outlined specifications, the component

values need to be carefully selected. The most important issue is the positioning of the 3 dB high-pass corner

f

–3 dB +

1

÷ 2π xR xCeq

Figure 18.

Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher

frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01

µF, which is not

inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal

frequency is 20 kHz, and R2 equals 1 k

Ω and R1 equals 50 Ω, the parallel capacitance of C1 and C2 must be

a minimum of 8 nF to avoid attenuating signals close to 20 kHz.

analog input, single-ended connection

converter will be at positive full scale when I/Q IN+ is at CML+0.5V (I/Q IN+ – I/Q IN– = 0.5 V) and will be at

negative full scale when I/Q IN+ is equal to CML – 0.5 V (I/Q IN+ – I/Q IN– = –0.5 V). Sufficient headroom must

be provided such that the input voltage never goes above 3.3 V or below AGND. The simplest way is to use

the dc bias source output (CML) of the THS0842.