TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

34

POST OFFICE BOX 1443

timing for IACK (see Notes 5 and Figure 28)

NO

’C32 - 40

’C32 - 50

’C32 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

63

td(H1H-IACKL)

Delay time, H1 high to IACK low

9

7

6

ns

64

td(H1H-IACKH)

Delay time, H1 high to IACK high

9

7

6

ns

NOTES:

5. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states.

H3

H1

IACK

A

D

63

64

Fetch IACK

Instruction

IACK Data

Read

Decode IACK

Instruction

Figure 28. IACK Timing