TMS320VC549 datasheet(15/60 Pages) TI

15 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

divide-by-two/divide-by-four clock option – PLL disabled

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle.

When an external clock source is used, the frequency injected must conform to specifications listed in the timing

requirements table.

switching

characteristics

over

recommended

operating

conditions

for

divide-by-two/

divide-by-four clock option – PLL disabled [H = 0.5tc(CO)] (see Figure 2 and Figure 3, and the

recommended operating conditions table)

PARAMETER

’549-80

’549-100

’549-120

UNIT

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

12.5‡

2tc(CI)

†

10‡

2tc(CI)

†

8.33‡

2tc(CI)

†

td(CIH-CO)

Delay time, X2/CLKIN high to

CLKOUT high/low

tf(CO)

Fall time, CLKOUT†

tr(CO)

Rise time, CLKOUT†

tw(COL)

Pulse duration, CLKOUT low†

H–3

H–1

H–2

H–1

H–2

H–1

tw(COH)

Pulse duration, CLKOUT high†

H–3

H–1

H–2

H–1

H–2

H–1

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

‡ It is recommended that the PLL clocking option be used for maximum frequency operation.

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