TMS320VC549 datasheet(16/60 Pages) TI

16 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

divide-by-two/divide-by-four clock option – PLL disabled (continued)

timing requirements for divide-by-two/divide-by-four clock option – PLL disabled (see Figure 3)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tc(CI)

Cycle time, X2/CLKIN

20‡

†

20‡

†

20‡

†

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

tw(CIL)

Pulse duration, X2/CLKIN low

†

tw(CIH) Pulse duration, X2/CLKIN high

†

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

‡ It is recommended that the PLL clocking option be used for maximum frequency operation.

tr(CO)

tf(CO)

CLKOUT

X2/CLKIN

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tc(CO)

tc(CI)

tw(COH)

tw(CIL)

tw(CIH)

Figure 3. External Divide-by-Two Clock Timing

TMS320VC549 데이터시트(PDF) 16 Page - Texas Instruments

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