PCS2I99448 datasheet(6/15 Pages) PULSECORE

6 / 15 page

September 2006

PCS2I99448

rev 0.4

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

6 of 15

Notice: The information in this document is subject to change without notice.

Table 8. AC CHARACTERISTICS (V

CC = 2.5V ± 5%, TA = –40°C to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

350

MHz

fMAX

Maximum Output Frequency

350

MHz

VPP

Peak-to-peak input voltage

PCLK

400

1000

LVPECL

VCMR

Common Mode Range

PCLK

1.2

VCC-0.8

LVPECL

tP, REF

Reference Input Pulse Width

1.4

tr, tf

CCLK Input Rise/Fall Time

1.0

0.8 to 2.0V

PCLK to any Q

1.5

4.2

tPLH/HL

Propagation delay

CCLK to any Q

1.7

4.4

tPLZ, HZ

Output Disable Time

tPZL, LZ

Output Enable Time

CCLK to CLK_STOP

0.0

Setup time

PCLK to CLK_STOP

0.0

CCLK to CLK_STOP

1.0

Hold time

PCLK to CLK_STOP

1.5

tsk(O)

Output-to-output Skew

150

tsk(PP)

Device-to-device Skew

PCLK or CCLK to any Q

2.7

tSK(p)

Output pulse skew

Using CCLK Using PCLK

200

300

fQ< 350 MHz and using CLK

DCQ

Output Duty Cycle

fQ<200 MHz and using PCLK

DCREF = 50%

tr, tf

Output Rise/Fall Time

0.1

1.0

0.6 to 1.8V

Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT.

2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR

range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP).

3. Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference

input pulse width, output duty cycle and maximum frequency specifications.

4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

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