PCM1795DB datasheet(41/58 Pages) TI

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System Clock (SCK) and Interface Timing

(BCH)

BCK

WDCK

(BCL)

(LB)

(BCY)

(DS)

(DH)

1.4 V

1.4V

(BL)

1.4V

DATA

DATAL

DATAR

PCM1795

www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009

The PCM1795 in an application using an external digital filter requires the synchronization of WDCK and the

system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK,

DATA, DATAL, and DATAR is shown in Figure 57 and Table 11.

Figure 57. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application

Table 11. Timing Characteristics for Figure 57

PARAMETER

MIN

MAX

UNIT

t(BCY)

BCK pulse cycle time

t(BCL)

BCK pulse duration, low

t(BCH)

BCK pulse duration, high

t(BL)

BCK rising edge to WDCK falling edge

t(LB)

WDCK falling edge to BCK rising edge

t(DS)

DATA, DATAL, DATAR setup time

t(DH)

DATA, DATAL, DATAR hold time

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