TUSB3200CPAH datasheet(76/93 Pages) TI

76 / 93 page

A–28

A.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH – Address FFE3h)

The adaptive clock generator MCLK capture register (high byte) contains the most significant byte of the 16-bit

CODEC master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs.

Bit

Mnemonic

CAP15

CAP14

CAP13

CAP12

CAP11

CAP10

CAP9

CAP8

Type

Default

BIT

MNEMONIC

NAME

DESCRIPTION

7:0

CAP(15:8)

ACG MCLK capture

The ACG MCLK capture bit values are updated by hardware each time a USB start

of frame occurs. This register contains the most signification byte of the 16-bit value.

A.5.3.6 Adaptive Clock Generator Divider Control Register (ACGDCTL – Address FFE2h)

The adaptive clock generator divider control register contains the control bits for programming the MCLKI signal

divider and the MCLKO signal divider. See section 2.2.10 for the operation details of the adaptive clock generator

and how to program these dividers.

Bit

Mnemonic

DIVM3

DIVM2

DIVM1

DIVM0

—

DIVI2

DIVI1

DIVI0

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

7:4

DIVM(3:0)

Divide by M value

The divide by M control bits are set by the MCU to program the MCLKO signal

divider.

0000b = divide by 1,

0001b = divide by 2,

…, 1111b = divide by 16

—

Reserved

Reserved for future use.

2:0

DIVI(2:0)

Divide by I value

The divide by I control bits are set by the MCU to program the MCLKI signal divider.

000b = divide by 1,

001b = divide by 2,

…,

111b = divide by 8

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