LPC2921 datasheet(2/83 Pages) NXP

2 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

2 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

I Other peripherals:

N Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide 8

analog inputs each with conversion times as low as 2.44

µs per channel. Each

channel provides a compare function to minimize interrupts.

N Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external

signal input.

N Four 32-bit timers each containing four capture-and-compare registers linked to

I/Os.

N Four six-channel PWMs (Pulse-Width Modulators) with capture and trap

functionality.

N Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.

N Quadrature encoder interface that can monitor one external quadrature encoder.

N 32-bit watchdog with timer change protection, running on safe clock.

I Up to 60 general-purpose I/O pins with programmable pull-up, pull-down, or bus

keeper.

I Vectored Interrupt Controller (VIC) with 16 priority levels.

I Up to 16 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up

features.

I Conﬁgurable clock out pin for driving external system clocks.

I Processor wake-up from power-down via external interrupt pins and CAN or LIN

activity.

I Flexible Reset Generator Unit (RGU) able to control resets of individual modules.

I Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual

modules:

N On-chip very low-power ring oscillator; ﬁxed frequency of 0.4 MHz; always on to

provide a Safe_Clock source for system monitoring.

N On-chip crystal oscillator with a recommended operating range from 10 MHz to

25 MHz. PLL input range 10 MHz to 25 MHz.

N On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.

N Generation of up to 11 base clocks.

N Seven fractional dividers.

I Second, dedicated CGU with its own PLL generates the USB clock and a conﬁgurable

clock output.

I Highly conﬁgurable system Power Management Unit (PMU):

N clock control of individual modules.

N allows minimization of system operating power consumption in any conﬁguration.

I Standard ARM test and debug interface with real-time in-circuit emulator.

I Boundary-scan test supported.

I ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for

application code and data storage.

I Dual power supply:

N CPU operating voltage: 1.8 V ± 5%.

N I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.

I 100-pin LQFP package.

I −40 °C to +85 °C ambient operating temperature range.

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