LPC2917SLASH01 datasheet(48/86 Pages) NXP

48 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

48 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

For generation of these base clocks, the CGU consists of primary and secondary clock

generators and one output generator for each base clock.

There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a

crystal oscillator. See Figure 12.

LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU0 itself and for

BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog

timer). To prevent the device from losing its clock source LP_OSC cannot be put into

power-down. The crystal oscillator can be used as source for high-frequency clocks or as

an external clock input if a crystal is not connected.

Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL

has three clock outputs: normal, 120

° phase-shifted and 240° phase-shifted.

Fig 12. Block diagram of the CGU0

400 kHz LP_OSC

PLL

FDIV0

EXTERNAL

OSCILLATOR

FDIV1

FDIV6

OUT 0

OUT 1

OUT 11

002aae147

clkout

clkout120

clkout240

CLOCK GENERATION UNIT (CGU0)

FREQUENCY

MONITOR

CLOCK

DETECTION

AHB TO DTL BRIDGE

BASE_SYS_CLK

BASE_ICLK1_CLK

OUT 3

BASE_IVNSS_CLK

OUT 2

BASE_PCR_CLK

BASE_SAFE_CLK

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