STA2500D datasheet(13/57 Pages) STMICROELECTRONICS

13 / 57 page

STA2500D

Pinout

Doc ID 16067 Rev 1

13/57

Pinout

Figure 2.

Pinout (bottom view)

4.1

Pin description and assignment

Table 13 shows the pin list of the STA2500D.

In columns “Reset” and “Default after reset”, the “PD/PU” shows the pads implementing an

internal pull-down/up.

The column “Reset” shows the state of the pins during hardware reset; the column “Default

after reset” shows the state of the pins after the hardware reset state is left, but before any

software parameter download.

The column “Type” describes the pin directions:

–

I for Input (All inputs have a Schmitt trigger function.)

–

O for Output

–

I/O for Input/Output

–

O/t for tri-state output

JTAG_TCK

GPIO_0

GPIO_3

7654321

BT_RESETN

BT_REF_CLK_IN

BT_LP_CLK

BT_HOST_WAKEUP

/BT_SPI_INT

BT_WAKEUP

BT_UART_TXD

/ BT_SPI_DO

BT_UART_RXD

/ BT_SPI_DI

BT_UART_CTS

/ BT_SPI_CLK

BT_VIO_B

BT_UART_RTS

/ BT_SPI_CS

BT_PCM_SYNC

BT_PCM_CLK

BT_PCM_A

BT_PCM_B

BT_GPIO_9

BT_VSSRF

BT_GPIO_10

BT_GPIO_11

BT_GPIO_16

BT_VSSANA

BT_CLK_REQ_IN_1

BT_CLK_REQ_IN_2

BT_CLK_REQ_OUT_1

BT_CONFIG_1

BT_CONFIG_3

BT_CONFIG_2

BT_RFP

BT_RFN

BT_HVA

BT_HVD

BT_VDD_D

BT_VIO_A

BT_VDD_CLD

BT_VDD_DSM

BT_VDD_N

BT_VDD_CL

BT_VDD_RF

BT_VSSDIG

BT_AF_PRG

BT_VSSANA

BT_TEST1

BT_TEST2

BT_CLK_REQ_OUT_2

BT_VSSRF

BT_GPIO_8

BT_GPIO_0

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