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STA2500D 데이터시트(PDF) 45 Page - STMicroelectronics

부품명 STA2500D
상세설명  Bluetooth??V2.1 EDR ("Lisbon") for automotive applications
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STA2500D 데이터시트(HTML) 45 Page - STMicroelectronics

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STA2500D
Digital interfaces
Doc ID 16067 Rev 1
45/57
Figure 22.
PCM interface timing
Table 27.
PCM interface parameters
Symbol
Description
Min.
Typ.
Max.
Unit
PCM Interface
FPCM_CLK Frequency of PCM_CLK (Slave)
128(1)
2048
4000(2)
kHz
FPCM_SYNC Frequency of PCM_SYNC
-
8
-
kHz
Psync_delay Delay of the starting of the first slot
0
-
255
cycles
Ss
Slot start (programmable for every slot)
0
-
255
cycles
D
Data size
8
-
16
bits
N
Number of slots per frame
1
-
3
-
1.
Note that it is not possible to use 16 bits in Slave case if pcm_clk is 128kHz. This is the only exception.
2.
In Master case, the maximum of PCM_CLK is 2048 kHz.
Table 28.
PCM interface timing (at PCM_CLK = 2048 kHz)
Symbol
Description
Min.
Typ.
Max.
Unit
tWCH
High period of PCM_CLK
200
-
-
ns
tWCL
Low period of PCM_CLK
200
-
-
ns
tWSH
High period of PCM_SYNC
200
-
-
ns
tSSC
Setup time, PCM_SYNC high to PCM_CLK low
100
-
-
ns
tSDC
Setup time, PCM_A/B input valid to PCM_CLK low
100
-
-
ns
tHCD
Hold time, PCM_CLK low to PCM_A/B input valid
100
-
-
ns
tDCD
Delay time, PCM_CLK high to PCM_A/B output valid
-
-
150
ns
D02TL557
PCM_CLK
tWCL
PCM_SYNC
PCM_A/B in
PCM_B/A out
MSB
MSB-1
MSB-2
MSB-3
MSB-4
MSB
MSB-1
MSB-2
MSB-3
MSB-4
tSSC
tWCH
tWSH
tHCD
tSDC
tDCD



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