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CY24242PVC 데이터시트(PDF) 6 Page - Cypress Semiconductor

부품명 CY24242PVC
상세설명  Laser Printer System Frequency Synthesizer
PDF  10 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY24242PVC 데이터시트(HTML) 6 Page - Cypress Semiconductor

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CY24242
Document #: 38-07268 Rev. *B
Page 6 of 10
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
.
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66/100MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency equal to the reference
provided at pins X1, X2
14.318
MHz
tR
Output Rise Edge Rate
0.5
–
2
V/ns
tF
Output Fall Edge Rate
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.5V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
––
3
ms
Zo
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
–40
–
Ω
USBCLK Clock Output (Lump Capacitance Test Load = 20 pF, VDDC =3.3V)
Parameter
Description
Test Condition/Comments
CPU = 66/100 MHz
Unit
Min.
Typ.
Max.
tR
Output Rise Edge Rate
0.5
–
2
V/ns
tF
Output Fall Edge Rate
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
tJL
Jitter, Long term
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
––
500
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
––
400
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
––3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
–40
–
Ω
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TA
Operating Temperature
–55 to +125
°C
TB
Ambient Temperature under Bias
0 to +70
°C
ESDPROT
Input ESD Protection
2 (min.)
kV



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