AD8120ACPZ-R2 datasheet(13/16 Pages) AD

부품명	AD8120ACPZ-R2

상세설명	Triple Skew-Compensating Video Delay Line with Analog and Digital Control

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AD8120

Rev. 0 | Page 13 of 16

SPI Timing

Figure 21 shows the SPI 2-byte timing sequence. Table 11 lists

the timing parameters for SPI.

SCK

SDI/SDO

C1 C0 X

X D5 D4 D3D2 D1D0

Figure 21. SPI 2-Byte Timing Sequence

t4 t5

SCK

SDI

R/W

Figure 22. SPI Timing Diagram

Table 11. SPI Timing Parameters

Parameter

Description

Setup time, CS to SCK

Clock pulse high, SCK

Clock pulse low, SCK

Setup time, SDI to SCK

Hold time, SDI to SCK

Hold time, SCK to CS

I2C Timing

Figure 23 shows the I2C 3-byte timing sequence. Table 12 lists

the timing parameters for I2C.

SDA

01 1 1 0

SCL

Figure 23. I2C 3-Byte Timing Sequence

SDA

SCL

t2 t

Figure 24. I2C Timing Diagram

Table 12. I2C Timing Parameters

Parameter

Description

Setup time, SDA to SCL

Clock pulse high, SCL

Clock pulse low, SCL

Setup time, SDA (input) to SCL

Hold time, SDA (input) to SCL

Hold time, SCL to SDA

AD8120ACPZ-R2 데이터시트(PDF) 13 Page - Analog Devices

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