ST7263BEX datasheet(54/186 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7263Bxx

54/186

Doc ID 7516 Rev 8

On-chip peripherals

11.1

Watchdog timer (WDG)

11.1.1

Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated

by external interference or by unforeseen logical conditions, which causes the application

program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on

expiry of a programmed time period, unless the program refreshes the counter’s contents

before the T6 bit becomes cleared.

11.1.2

Main features

●

Programmable free-running counter (64 increments of 49,152 CPU cycles)

●

Programmable reset

●

Reset (if watchdog activated) when the T6 bit reaches zero

●

Optional reset on HALT instruction (configurable by option byte)

●

Hardware Watchdog selectable by option byte.

11.1.3

Functional description

The counter value stored in the CR register (bits T6:T0), is decremented every 49,152

machine cycles, and the length of the timeout period can be programmed by the user in 64

increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls

over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle by driving low the reset

pin for tW(RSTL)out (see Table 72).

The application program must write in the CR register at regular intervals during normal

operation to prevent an MCU reset. This down counter is free-running: it counts down even if

the watchdog is disabled. The value to be stored in the CR register must be between FFh

and C0h (see Table 17):

●

The WDGA bit is set (watchdog enabled)

●

The T6 bit is set to prevent generating an immediate reset

●

The T5:T0 bits contain the number of increments which represents the time delay

before the watchdog produces a reset.

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