전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

STM32F107RC 데이터시트(PDF) 56 Page - STMicroelectronics

부품명 STM32F107RC
상세설명  Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces
PDF  95 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F107RC 데이터시트(HTML) 56 Page - STMicroelectronics

Back Button STM32F107RC Datasheet HTML 52Page - STMicroelectronics STM32F107RC Datasheet HTML 53Page - STMicroelectronics STM32F107RC Datasheet HTML 54Page - STMicroelectronics STM32F107RC Datasheet HTML 55Page - STMicroelectronics STM32F107RC Datasheet HTML 56Page - STMicroelectronics STM32F107RC Datasheet HTML 57Page - STMicroelectronics STM32F107RC Datasheet HTML 58Page - STMicroelectronics STM32F107RC Datasheet HTML 59Page - STMicroelectronics STM32F107RC Datasheet HTML 60Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 56 / 95 page
background image
Electrical characteristics
STM32F105xx, STM32F107xx
56/95
Doc ID 15274 Rev 4
Figure 17.
I/O AC characteristics definition
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 35).
Unless otherwise specified, the parameters given in Table 38 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
ai14131
10%
90%
50%
tr(IO)out
OUTPUT
EXT ERNAL
ON 50pF
Maximum fr equency is achieved if (tr + tf) "2/3)T and if the duty cycle is (45-55%)"
10%
50%
90%
when loaded by 50pF
T
tr(IO)out
Table 38.
NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage
–0.5
0.8
V
VIH(NRST)
(1)
NRST Input high level voltage
2
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
200
mV
RPU
Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum
(~10% order)
.
VIN ?"VSS
30
40
50
kY
VF(NRST)
(1)
NRST Input filtered pulse
100
ns
VNF(NRST)
(1)
NRST Input not filtered pulse
VDD > 2.7 V
300
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com