STM8L151C4U6 datasheet(77/101 Pages) STMICROELECTRONICS

77 / 101 page

STM8L151xx, STM8L152xx

Electrical parameters

Doc ID 15962 Rev 2

77/101

8.3.7

Communication interfaces

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in Table 37 are derived from tests

performed under ambient temperature, fSYSCLK frequency and VDD supply voltage

conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on

the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 37.

SPI1 characteristics

Symbol

Parameter

Conditions(1)

Parameters are given by selecting 10 MHz I/O output frequency.

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

TBD

tsu(NSS)

(2)

Values based on design simulation and/or characterization results, and not tested in production.

NSS setup time

Slave mode

4 x 1/fSYSCLK

th(NSS)

(2)

NSS hold time

Slave mode

TBD

tw(SCKH)

(2)

tw(SCKL)

(2)

SCK high and low time

Master mode,

fSYSCLK = 8 MHz, fSCK= 4 MHz

TBD

tsu(MI)

(2)

tsu(SI)

(2)

Data input setup time

Master mode

TBD

Slave mode

TBD

th(MI)

(2)

th(SI)

(2)

Data input hold time

Master mode

TBD

Slave mode

TBD

ta(SO)

(2)(3)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Data output access time

Slave mode

3x 1/fSYSCLK

tdis(SO)

(2)(4)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Data output disable time

Slave mode

TBD

tv(SO)

(2)

Data output valid time

Slave mode (after enable edge)

TBD

tv(MO)

(2)

Data output valid time

Master mode (after enable

edge)

-TBD

th(SO)

(2)

Data output hold time

Slave mode (after enable edge)

TBD

th(MO)

(2)

Master mode (after enable

edge)

TBD

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