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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MCP4728 데이터시트(PDF) 9 Page - Microchip Technology |
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MCP4728 데이터시트(HTML) 9 Page - Microchip Technology |
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9 / 66 page  © 2009 Microchip Technology Inc. DS22187C-page 9 MCP4728 SCL Rise Time (Note 1) TRSCL — — 1000 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 80 ns High Speed Mode 1.7 20 — 160 ns High Speed Mode 1.7 (Note 2) 10 — 40 ns High Speed Mode 3.4 10 — 80 ns High Speed Mode 3.4 (Note 2) SDA Rise Time (Note 1) TRSDA — — 1000 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 80 ns High Speed Mode 1.7 10 — 40 ns High Speed Mode 3.4 SCL Fall Time (Note 1) TFSCL — — 300 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 160 ns High Speed Mode 1.7 10 — 80 ns High Speed Mode 3.4 SDA Fall Time (Note 1) TFSDA — — 300 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 160 ns High Speed Mode 1.7 10 — 80 ns High Speed Mode 3.4 Data Input Setup Time TSU:DAT 250 — — ns Standard Mode 100 — — ns Fast Mode 10 — — ns High Speed Mode 1.7 10 — — ns High Speed Mode 3.4 Data Hold Time (Input, Output) (Note 3) THD:DAT 0 — 3450 ns Standard Mode 0 — 900 ns Fast Mode 0 — 70 ns High Speed Mode 1.7 0 — 150 ns High Speed Mode 3.4 Output Valid from Clock (Note 4) TAA 0 — 3750 ns Standard Mode 0 — 1200 ns Fast Mode 0 — 150 ns High Speed Mode 1.7 0 — 310 ns High Speed Mode 3.4 Bus Free Time (Note 5) TBUF 4700 — — ns Standard Mode 1300 — — ns Fast Mode — — — ns High Speed Mode 1.7 — — — ns High Speed Mode 3.4 Input Filter Spike Suppression (SDA and SCL) (Not Tested) TSP — — — ns Standard Mode, (Not Applicable) — 50 — ns Fast Mode — 10 — ns High Speed Mode 1.7 — 10 — ns High Speed Mode 3.4 I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for T A = -40 to +125°C, VSS = 0V, Standard and Fast Mode: VDD = +2.7V to +5.5V High Speed Mode: VDD = +4.5V to +5.5V. Parameters Sym Min Typ Max Units Conditions Note 1: This parameter is ensured by characterization and is not 100% tested. 2: After a Repeated Start condition or an Acknowledge bit. 3: If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than t SP. Data Output: This parameter is characterized, and tested indirectly by testing T AA parameter. 4: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA). 5: Time between Start and Stop conditions. |
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