MIC3003 datasheet(56/75 Pages) MICREL

56 / 75 page

Micrel, Inc.

MIC3003

November 2009

M9999-111209-C

hbwhelp@micrel.com or (408) 955-1690

OEM Configuration Register 0 (OEMCFG0)

D[7]

RST

write only

D[6]

QGPOS

read/write

D[5]

DFLT

read-only

D[4]

reserved

D[3]

MODREF

reserved

D[2]

VAUX[2]

read/write

D[1]

VAUX[1]

read/write

D[0]

VAUX[0]

read/write

Default value

0000 0000b = 00h

Serial address

A6h

Byte address

00 = 00h

A write to OEMCFG0 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a

new conversion sequence once the write operation is complete.

All bits in OEMCFG0 are non-volatile except DFLT and RST. A valid OEM password is required for access to this register.

Bit(s)

Function

Operation

D[7]

RST

0 = no action; 1 = reset

Issuing a software reset by setting RST high is equivalent to

a full power cycle of the MIC3003.

D[6]

QGPOS

Determines the state of QGPO in

GPO mode

If OEMCFG3 bit 7 (QGPOM) is low, this bit determines

whether the QGPO output is high (undriven) or low (driven-

open-drain).

If QGPOM is high (Reset mode), this bit has no function

D[5]

DFLT

Diode fault flag.

1 = diode fault; 0 = OK.

D[4]

Output enable for SHDN, VMOD,

and VBIAS.

1 = enabled; 0 = hi-Z

D[3]

MODREF

Selects whether VMOD is

referenced to ground or VDD.

1 = VDD; 0 = GND

D[2:0]

VAUX[2:0]

Selects the voltage reported in

VINh:VINl.

000 = VIN

001 = VDDA

010 = VBIAS

011 = VMOD

100 = APCDAC

101 = MODDAC

110 = FLTDAC

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