56F8167 datasheet(21/182 Pages) FREESCALE

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Signal Pins

56F8367 Technical Data, Rev. 9

Freescale Semiconductor

Preliminary

(GPIOE2)

Output

Schmitt

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Address Bus — A6 - A7 specify two of the address lines for

external program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

Port E GPIO — These two GPIO pins can be individually

programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOE_PUR register.

Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.

(GPIOE3)

(GPIOA0)

Output

Schmitt

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Address Bus— A8 - A15 specify eight of the address lines for

external program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

Port A GPIO — These eight GPIO pins can be individually

programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOA_PUR register.

Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.

(GPIOA1)

A10

(GPIOA2)

A11

(GPIOA3)

A12

(GPIOA4)

A13

(GPIOA5)

A14

(GPIOA6)

A15

(GPIOA7)

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

56F8167 데이터시트(PDF) 21 Page - Freescale Semiconductor, Inc

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