56F8167 datasheet(49/182 Pages) FREESCALE

49 / 182 page

EOnCE Memory Map

56F8367 Technical Data, Rev. 9

Freescale Semiconductor

Preliminary

4.6 EOnCE Memory Map

4.7 Peripheral Memory Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may

be accessed with the same addressing modes used for ordinary Data memory, except all peripheral

registers should be read/written using word accesses only.

Table 4-8 EOnCE Memory Map

Address

Reserved

X:$FF FF8A

OESCR

External Signal Control Register

Reserved

X:$FF FF8E

OBCNTR

Breakpoint Unit [0] Counter

Reserved

X:$FF FF90

OBMSK (32 bits)

Breakpoint 1 Unit [0] Mask Register

X:$FF FF91

—

Breakpoint 1 Unit [0] Mask Register

X:$FF FF92

OBAR2 (32 bits)

Breakpoint 2 Unit [0] Address Register

X:$FF FF93

—

Breakpoint 2 Unit [0] Address Register

X:$FF FF94

OBAR1 (24 bits)

Breakpoint 1 Unit [0] Address Register

X:$FF FF95

—

Breakpoint 1 Unit [0] Address Register

X:$FF FF96

OBCR (24 bits)

Breakpoint Unit [0] Control Register

X:$FF FF97

—

Breakpoint Unit [0] Control Register

X:$FF FF98

OTB (21-24 bits/stage)

Trace Buffer Register Stages

X:$FF FF99

—

Trace Buffer Register Stages

X:$FF FF9A

OTBPR (8 bits)

Trace Buffer Pointer Register

X:$FF FF9B

OTBCR

Trace Buffer Control Register

X:$FF FF9C

OBASE (8 bits)

Peripheral Base Address Register

X:$FF FF9D

OSR

Status Register

X:$FF FF9E

OSCNTR (24 bits)

Instruction Step Counter

X:$FF FF9F

—

Instruction Step Counter

:X:$FF FFA0

OCR (bits)

Control Register

Reserved

X:$FF FFFC

OCLSR (8 bits)

Core Lock / Unlock Status Register

X:$FF FFFD

OTXRXSR (8 bits)

Transmit and Receive Status and Control Register

X:$FF FFFE

OTX / ORX (32 bits)

Transmit Register / Receive Register

X:$FF FFFF

OTX1 / ORX1

Transmit Register Upper Word

Receive Register Upper Word

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