ICS8430-62 Datasheet

500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS8430AY-62 REVISION A JULY 2, 2009

4

©2009 Integrated Device Technology, Inc.

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

↑ = Rising edge transition

↓ = Falling edge transition

Table 3B. Programmable VCO Frequency Function Table

NOTE 1: These M divide values and the resulting frequencies correspond to a REF_CLK or crystal frequency of 16MHz.

Inputs

Conditions

MR

nP_LOAD

M

N

S_LOAD

S_CLOCK

S_DATA

H

X

X

X

X

X

X

Reset. Forces true outputs LOW.

L

L

Data

Data

X

X

X

Data on M and N inputs passed directly to the M divider

and N output divider. TEST output forced LOW.

L

↑

Data

Data

L

X

X

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

LH

X

X

L

↑

Data

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

LH

X

X

↑

LData

Contents of the shift register are passed to the

M divider and N output divider.

LH

X

X

↓

L

Data

M divider and N output divider values are latched.

L

H

X

X

L

X

X

Parallel or serial input do not affect shift registers.

LH

X

X

H

↑

Data

S_DATA passed directly to M divider as it is clocked.

VCO Frequency

(MHz)

M Divide

256

128

64

32

16

8421

M8

M7

M6

M5

M4

M3

M2

M1

M0

250

250

011111010

251

251

011111011

252

252

011111100

253

253

011111101

•

•

••••••

•••

•

•

••••••

•••

498

498

111110010

499

499

111110011

500

500

111110100