ICS8430-62 Datasheet

500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS8430AY-62 REVISION A JULY 2, 2009

13

©2009 Integrated Device Technology, Inc.

Recommendations for Unused Input and Output Pins

Inputs:

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k

Ω resistor can be tied from

XTAL_IN to ground.

REF_CLK Input

For applications not requiring the use of the reference clock, it can be

left floating. Though not required, but for additional protection, a 1k

Ω

resistor can be tied from the REF_CLK to ground.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k

Ω resistor can be used.

Outputs:

TEST Output

The unused TEST output can be left floating. There should be no

trace attached.

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Ω

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 5A and 5B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 5A. 3.3V LVPECL Output Termination

Figure 5B. 3.3V LVPECL Output Termination

3.3V

V

R1

50

Ω

R2

50

Ω

RTT

Z

Z

+

_

RTT =

* Z

o

1

((V

3.3V

LVPECL

Input

R1

84

Ω

R2

84

Ω

3.3V

R3

125

Ω

R4

125

Ω

Z

Z

LVPECL

Input

3.3V

3.3V

+

_