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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATmega128 데이터시트(PDF) 92 Page - ATMEL Corporation |
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ATmega128 데이터시트(HTML) 92 Page - ATMEL Corporation |
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92 / 386 page  92 2467S–AVR–07/09 ATmega128 External Interrupt Mask Register – EIMSK • Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter- rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. External Interrupt Flag Register – EIFR • Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 70 for more information. Bit 765 4321 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 Bit 765 4321 0 INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 |
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