ATmega128 datasheet(21/386 Pages) ATMEL

21 / 386 page

2467S–AVR–07/09

ATmega128

Data Memory Access

Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

EEPROM Data

Memory

The ATmega128 contains 4K bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

“Memory Programming” on page 286 contains a detailed description on EEPROM programming

in SPI, JTAG, or Parallel Programming mode

EEPROM Read/Write

Access

The EEPROM access registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 2. A self-timing function, however, lets

the user software detect when the next byte can be written. If the user code contains instructions

that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V

is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time

to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-

ing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

EEPROM Address

EEARL

• Bits 15..12 – Res: Reserved Bits

These are reserved bits and will always read as zero. When writing to this address location,

write these bits to zero for compatibility with future devices.

clk

Data

Address

Address valid

Compute Address

CPU

Memory access instruction

Next instruction

Bit

15141312

–

EEAR11

EEAR10

EEAR9

EEAR8

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

654

Read/Write

R/W

Initial Value

XXX

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