ATmega128 datasheet(192/386 Pages) ATMEL

192 / 386 page

192

2467S–AVR–07/09

ATmega128

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(character size) in a frame the Receiver and Transmitter use.

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when Asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

USART Baud Rate

Registers – UBRRnL

and UBRRnH

UBRRnH is not available in mega103 compatibility mode

Table 79. USBSn Bit Settings

USBSn

Stop Bit(s)

01-bit

12-bits

Table 80. UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

000

5-bit

001

6-bit

010

7-bit

011

8-bit

100

Reserved

101

Reserved

110

Reserved

111

9-bit

Table 81. UCPOLn Bit Settings

UCPOLn

Transmitted Data Changed (Output of

TxDn Pin)

Received Data Sampled (Input on

RxDn Pin)

Rising XCKn Edge

Falling XCKn Edge

Rising XCKn Edge

Bit

151413121110

–

UBRRn[11:8]

UBRRnH

UBRRn[7:0]

UBRRnL

765

4321

Read/Write

R/W

Initial Value

000

0000

000

0000

ATmega128 데이터시트(PDF) 192 Page - ATMEL Corporation

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