ATmega128 datasheet(299/386 Pages) ATMEL

299 / 386 page

299

2467S–AVR–07/09

ATmega128

Figure 142. Parallel Programming Timing, Loading Sequence with Timing Requirements

Note:

The timing requirements shown in Figure 141 (i.e. tDVXH, tXHXL, and tXLDX) also apply to loading

operation.

Figure 143. Parallel Programming Timing, Reading Sequence (Within the Same Page) with

Timing Requirements

Note:

The timing requirements shown in Figure 141 (i.e. tDVXH, tXHXL, and tXLDX) also apply to reading

operation.

Table 126. Parallel Programming Characteristics, V

CC = 5 V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

IPP

Programming Enable Current

250

μA

tDVXH

Data and Control Valid before XTAL1 High

tXLXH

XTAL1 Low to XTAL1 High

200

tXHXL

XTAL1 Pulse Width High

150

tXLDX

Data and Control Hold after XTAL1 Low

tXLWL

XTAL1 Low to WR Low

XTAL1

PAGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

XTAL1

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BHDV

OLDV

XLOL

OHDZ

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